The present invention relates generally to bipolar transistors and more specifically to bipolar transistors having a buried subcollector structure.
Bipolar transistors are generally built with a low impurity concentration collector region. To reduce the collector resistance, a subcollector is usually provided in the bottom of the collector region and spaced from the base region to allow a low resistance path for connection to the top of the collector. In circuits wherein the collector is junction isolated from the substrate in which it is built, the buried collector region is provided to reduce the current gain of the parasitic substrate transistor which is formed between the base collector and the substrate regions. The lateral isolation in these circuits may either be junction, dielectric or a combination of junction and dielectric.
The general method of forming the buried region is to introduce impurities into the base region before the formation of the collector layer which may be formed for example, by epitaxial deposition. This results in the diffusion down into the substrate region as well as to some updiffusion into the epitaxial layer. The subcollector region is driven deep into the substrate to maintain a desired sheet resistance of a reasonable impurity concentration at the collector-substrate junction or interface. For a collector layer having a thickness of approximately 1.6 microns, the general diffusion depth of the buried collector region into the substrate is approximately 3.37 microns. With such deep drive-in of the subcollector into the substrate, a substantial amount of space must be left between the lateral isolation and the subcollector region because of lateral diffusion which takes place during the deep drive-in. To assure a minimum spacing of 1.5 microns between the edge of the subcollector and the lateral diffusion, the spacing between the mask periphery of each of these two areas has generally been about 5 microns.
It should also be noted that the collector to substrate capacitance of the junction isolated IC's has two major components. The first, is the isolation diffusion to epitaxial layer, and the second is the subcollector to substrate capacitance components. Since the isolation diffusion in oxide isolated IC's is totally or partially replaced by oxide, the isolation diffusion to epitaxial layer capacitance is greatly reduced or eliminated. But for either of the processes, since the subcollector is diffused into the substrate, the subcollector to substrate capacitance is the sum of the sidewall and floor capacitance terms. The sidewall component of the subcollector to substrate capacitance is directly proportional to the peripheral area of the subcollector-substrate junction, which is determined by the subcollector mask dimensions and lateral and vertical junction depths of the subcollector into the substrate. On the other hand, the floor term is only directly proportional to the subcollector mask area.
As a result, the total subcollector to substrate capacitance can be quite accurately expressed analytically as EQU C.sub.subc.-subs. =C(X.sub.m Y.sub.m +.pi.(X.sub.m +Y.sub.m)X.sub.j +2.pi.X.sub.j.sup.2) (1)
where C, X.sub.m, Y.sub.m, X.sub.j, are subcollector to substrate capacitance per unit area, subcollector mask dimension in X and Y directions, and subcollector junction depth into the substrate measured from the epi-substrate interface, respectively. In deriving expression (1), it is assumed that the substrate is uniformly doped, the curved junction effects are negligible and lateral diffusion junction depth is equal to the vertical junction depth X.sub.j. It should be noted that these assumptions hold quite well under general bipolar IC manufacturing processes.
As can be seen from (1), as the mask dimensions get smaller, the sidewall term will gain more importance in determining the total subcollector to substrate capacitance. Since the collector to substrate capacitance of the oxide isolated IC's is essentially determined by the subcollector to substrate capacitance, the sidewall capacitance becomes even more important compared to junction isolated IC's.
An object of the present invention is to provide a subcollector structure which allows increase of packing density.
Another object of the present invention is to provide a subcollector structure which reduces the subcollector to substrate capacitance.
Still another object of the present invention is to provide an improved subcollector structure which allows increased packing density and reduced subcollector to substrate capacitance requiring a minimum number of additional processing steps.
These and other objects are attained by forming a subcollector as a two-segment collector having a thick portion and a thin portion. The thick portion extends laterally between the projection of the emitter region onto the junction between the collector region and the substrate and a collector contact region which extends from the surface of the collector down to the buried subcollector region. The thin subcollector portion extends laterally from the thick portion towards tne lateral isolation of the collector region but spaced from the lateral isolation. The depth of the thick portions is substantially greater than that of the thin portion. Since the thin portion is adjacent to the lateral isolation, the side diffusion is substantially smaller than that for the deep portion and therefore the initial spacing in the mask is reduced thereby increasing packing density. Also, since peripheral area of the subcollector-substrate junction is decreased, the collector to substrate capacitance is reduced. The analytical expression for calculating the total subcollector to substrate capacitance of the structure explained, can be written as follows, assuming the same assumptions hold as in deriving expression (1), ##EQU1## Where, C, X.sub.M, Y.sub.M, X.sub.J, X.sub.JSH, X.sub.MDD, Y.sub.MDD are the subcollector to substrate capacitance per unit area, subcollector mask dimension in X and Y directions, deep and shallow subcollector junction depths into the substrates, both measured from the epi-substrate interface, and deep subcollector mask dimension in X and Y directions, respectively.
As can be seen from expression (2), the key factors in determining the capacitance reductions are X.sub.JSH /X.sub.j and (X.sub.m +Y.sub.M)/(X.sub.MDD +Y.sub.MDD), or in other words the shallow to deep junction depth, and total subcollector peripheral to deep subcollector peripheral length ratios. It should also be noted that the total capacitance reduction increases as the total subcollector dimensions get smaller.
The lateral isolation may be a diffused junction region which extends from the surface of the collector down into the substrate or may be a buried junction isolated region (channel -stop) covered by a dielectric isolated region extending from the buried junction isolated region to the surface of the collector. In either case, the thin portion of the subcollector has a thickness at least as great as that of the lateral isolation region extending into the substrate.
The method of fabricating the new and improved subcollector region includes: masking the substrate of a first conductivity type and introducing second conductivity type impurities to define the thick portion of the subcollector; partially diffusing the impurities into the substrate; forming an additional mask to form the remainder or the thin portion of the subcollector region and introducing second conductivity type impurities to define the thin portion; providing a third mask which defines the buried portion of the lateral junction isolation and introducing first conductivity type impurities and forming an epitaxial layer of the second conductivity type on the substrate. The processing to form the bipolar transistors and its lateral isolation is the same as that of any other bipolar transistor.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.